Non-volatile memory is a type of memory that preserves data with or without power applied to the memory. Most computer and electronic systems use a binary number system with bits. Two distinctly different current levels that flow through the memory under the correct conditions represent each bit, a one or a zero.
Some memory is single-level, where one bit of information is stored in each memory cell. In order to determine the value of the memory cell, current through the memory cell is compared to a reference memory cell. A current through the memory cell that is lower than that through the reference cell represents one bit value, while a current through the memory cell that is higher than that through the reference cell represents the other bit value.
In advanced memory devices, it is desirable to simultaneously perform multiple operations on memory, for example read while writing, or read while erasing. In order to achieve this, a memory device is organized into smaller blocks of memory called ‘banks.’ One operation may be performed on one bank while another operation is performed on another bank.
In one memory architecture, a set of sense amplifiers handles ‘read’ operations for the banks of memory and another set of sense amplifiers handles ‘verify’ operations for the banks. The offset between the two sets of amplifiers reduces current within the memory device and causes associated performance problems.
FIG. 1 is a schematic diagram illustrating one solution to this problem with conventional system 90. System 90 is a non-volatile memory with memory banks 100 connected to Y-decoder and sense amplifier circuit 102, and to X-decoder circuit 104. Rather than having only two sets of amplifiers, as in previously described memory architecture, each memory bank 100 has amplifier circuit 102.
In order to read a memory cell (see FIG. 2) from memory bank 100, bias circuit 103 activates a reference cell current from reference matrix 101. The reference cell current is mirrored from reference matrix 101 through bias circuit 103 to amplifier circuit 102. Amplifier circuit 102 compares the reference cell current to a memory cell current through memory bank 100 in order to determine the value in a memory cell.
FIG. 2 is a schematic diagram illustrating components of conventional system 90 from FIG. 1. Bias circuit 103 includes transistor 110, which, during a memory read, for example, activates reference matrix 101. Reference matrix 101 includes transistors 112 and 114. Transistor 114 is also activated during a memory read, which causes a reference cell current to flow through reference cell 118. Cell 116 is used during verify operations. Current through reference cell 118 flows through transistor 120 and is mirrored by transistor 122, and caused to flow through transistor 124.
In Y-decoder and amplifier circuit 102, transistor 126 mirrors reference cell current and causes it to flow through transistor 128. As part of the memory read operation, memory block 100 with memory cell 130 is biased by transistor 132, causing current to flow, with a voltage drop across transistors 132 and memory cell 130, and other associated components that are not illustrated for simplicity. Sense amplifier 134 compares the current through (or voltage across) memory cell 130 with the current through reference cell 118. The bit value stored in memory cell 130 is related to the current through memory cell 130 relative to current through reference cell 118.
One problem with conventional system 90 is that it takes a large amount of space to implement (it has a large “footprint”). Another problem is that it takes a significant amount of time to test conventional system 90.
Accordingly, what is needed is a system and method for avoiding offset, reducing the footprint and decreasing test time in a non-volatile memory. The present invention addresses such a need.